Deterministic Computations on a PRAM with Static Processor and Memory Faults

We consider Parallel Random Access Machine (PRAM) which has some processors and memory cells faulty. The faults considered are static, i.e., once the machine starts to operate, the operational/faulty status of PRAM components does not change. We develop a deterministic simulation of a fully operational PRAM on a similar faulty machine which has constant fractions of faults among processors and memory cells. The simulating PRAM has n processors and m memory cells, and simulates a PRAM with n processors and a constant fraction of m memory cells. The simulation is in two phases: it starts with preprocessing, which is followed by the simulation proper performed in a step-by-step fashion. Preprocessing is performed in time O((mn + log n) log n). The slowdown of a step-by-step part of the simulation is O(logm). This work was published as [13]. The results of this paper appeared in a preliminary form in [12]. Department of Computer Science and Engineering, University of Colorado Denver, Denver, CO 80217, USA. Work supported by the National Science Foundation under Grant No. 0310503. Department of Computer Science, University of Liverpool, Liverpool L69 3BX, United Kingdom. Work supported by the EPSRC grant GR/N09855/01. §Département d’informatique et d’ingénierie, Université du Québec en Outaouais, Gatineau, Québec J8X 3X7, Canada. Work supported by the NSERC grant 0008136. ar X iv :1 80 1. 00 23 7v 1 [ cs .D C ] 3 1 D ec 2 01 7